1. Field of the Invention
The invention relates to an epitaxially coated silicon wafer and to a method for producing epitaxially coated silicon wafers.
2. Background Art
Epitaxially coated silicon wafers are suitable for use in the semiconductor industry, in particular for the fabrication of large scale integrated electronic components such as e.g. microprocessors or memory chips. Starting materials (substrates) for modern microelectronics are required to meet stringent requirements with respect to global and local flatness, thickness distribution, single-side-referenced local flatness (nanotopology) and freedom from defects.
Global flatness relates to the entire surface of a semiconductor wafer minus an edge exclusion to be defined. It is described by the GBIR (“global backsurface-referenced ideal plane/range”=magnitude of the positive and negative deviation from a backside-referenced ideal plane for the entire front side of the semiconductor wafer), which corresponds to the TTV (“total thickness variation”) specification that was formerly customary.
The LTV (“local thickness variation”) specification that was formerly customary is nowadays designated according to the SEMI standard by SBIR (“site backsurface-referenced ideal plane/range”=magnitude of the positive and negative deviation from a backside-referenced ideal plane for an individual component area defined dimension) and corresponds to the GBIR or TTV of a component area (“site”). Therefore, in contrast to the global flatness GBIR, the SBIR is referenced to defined fields on the wafer, that is to say for example to segments of an area grid of measurement windows having a size of 26×8 mm2 (site geometry). The maximum site geometry value SBIRmax specifies the maximum SBIR value for the component areas taken into account on a silicon wafer.
Maximum site-referenced flatness or geometry values such as the SBIRmax are usually determined taking account of a certain edge exclusion (EE=“edge exclusion”) of 3 mm, by way of example. An area on a silicon wafer within a nominal edge exclusion is usually referred to as the “Fixed Quality Area”, abbreviated as FQA. Those sites which have part of their area lying outside the FQA, but the center of which lies within the FQA, are called “partial sites”. The determination of the maximum local flatness often does not involve using the “partial sites”, but rather only the so-called “full sites”, that is to say the component areas lying completely within the FQA. In order to be able to compare maximum flatness values, it is essential to specify the edge exclusion and thus the size of the FQA and furthermore to specify whether or not the “partial sites” have been taken into account.
Furthermore, with regard to optimizing costs, it is frequently customary nowadays not to reject a silicon wafer owing, for example, only to a component area that exceeds the SBIRmax value specified by the component manufacturer, but rather to permit a defined percentage, e.g. 1%, of component areas to have higher values. The percentage of the sites which lie or are permitted to lie below a specific limit value of a geometry parameter is usually specified by a PUA (“Percent Useable Area”) value, which, e.g. in the case of an SBIRmax of less than or equal to 0.7 μm and a PUA value of 99%, indicates that 99% of the sites have an SBIRmax of less than or equal to 0.7 μm while higher SBIR values are also permitted for 1% of the sites (“chip yield”).
According to the prior art, a silicon wafer can be produced by a process sequence of separating a single crystal of silicon into wafers, rounding the mechanically sensitive edges, carrying out an abrasive step such as grinding or lapping followed by polishing. EP 547894 A1 describes a lapping method; grinding methods are described in applications EP 272531 A1 and EP 580162 A1.
The final flatness is generally produced by the polishing step, which may be preceded, if appropriate, by an etching step for removing disturbed crystal layers and for removing impurities. A suitable etching method is known from DE 19833257 C1, by way of example. Traditional single-side polishing methods generally lead to poorer plane-parallelisms, while polishing methods acting on both sides (“double side polishing”) make it possible to produce silicon wafers with improved flatness.
In the case of polished silicon wafers, therefore, an attempt is made to achieve the required flatness by suitable processing steps such as grinding, lapping and polishing.
However, the polishing of a silicon wafer usually gives rise to a decrease in the thickness of the planar silicon wafer toward the edge (“edge roll-off”). Etching methods also tend to attack the silicon wafer to a greater extent at the edge and also to produce such an edge roll-off. In order to counteract this, it is customary for silicon wafers to be polished concavely. A concavely polished silicon wafer is thinner in the center, then increases in its thickness toward the edge, and has a decrease in thickness in an outer edge region.
DE 19938340 C1 describes depositing a monocrystalline layer on monocrystalline silicon wafers, the deposited layer being made of silicon with the same crystal orientation, a so-called epitaxial layer, on which semiconductor components are applied later. Systems of this type have certain advantages over silicon wafers made of homogeneous material, for example the prevention of charge reversal in bipolar CMOS circuits followed by the short circuiting of the component (“latch-up”), lower defect densities (for example reduced number of COPs (“crystal-originated particles”) and also the absence of an appreciable oxygen content, whereby it is possible to preclude short-circuit risk due to oxygen precipitates in component-relevant regions.
According to the prior art, epitaxially coated silicon wafers are produced from suitable intermediates by means of a process sequence of removal polishing-final polishing-cleaning-epitaxy.
DE 10025871 A1, for example, discloses a method for producing a silicon wafer with an epitaxial layer deposited on its front side, the method comprising the following process steps:    (a) a removal polishing step as the sole polishing step;    (b) (hydrophilic) cleaning and drying of the silicon wafer;    (c) pretreatment of the front side of the silicon wafer at a temperature of 950 to 1250 degrees Celsius in an epitaxy reactor; and    (d) deposition of an epitaxial layer on the front side of the pretreated silicon wafer.
It is customary, in order to protect silicon wafers from particle loading, to subject the silicon wafers to a hydrophilic cleaning after polishing. The hydrophilic cleaning produces native oxide on the front and rear sides of the silicon wafer which is very thin (approximately 0.5-2 nm, depending on the type of cleaning and measurement). This native oxide is removed in the course of a pretreatment in an epitaxy reactor under a hydrogen atmosphere (also called “H2 bake”).
In a second step, the surface roughness of the front side of the silicon wafer is reduced and polishing defects are removed from the surface by usually small amounts of an etching medium, for example gaseous hydrogen chloride (HCl) being added to a hydrogen atmosphere.
Sometimes, besides an etching medium such as HCl, a silane compound, for example silane (SiH4), dichlorosilane (SiH2Cl2), trichlorosilane (TCS, SiHCl3) or tetrachlorosilane (SiCl4), is also added to the hydrogen atmosphere in an amount such that silicon deposition and silicon etching removal are in equilibrium. Both reactions proceed at a sufficiently high reaction rate, however, so that silicon on the surface is mobile and the surface is smoothed and defects are removed on the surface.
Epitaxy reactors, which are used in particular in the semiconductor industry for the deposition of an epitaxial layer on a silicon wafer, are described in the prior art. During all coating or deposition steps, one or more silicon wafers are heated by means of heating sources, preferably by means of upper and lower heating sources, for example lamps or lamp banks, and subsequently exposed to a gas mixture comprising a source gas, a carrier gas and, if appropriate, a doping gas.
A susceptor, which comprises graphite, SiC or quartz, for example, serves as a support for the silicon wafer in a process chamber of the epitaxy reactor. During the deposition process, the silicon wafer rests on this susceptor or in milled-out portions of the susceptor in order to ensure a uniform heating and to protect the rear side of the silicon wafer, on which usually there is no deposition, from the source gas. In accordance with the prior art, the process chambers are designed for one or more silicon wafers.
In the case of silicon wafers having relatively large diameters (greater than or equal to 150 mm), single wafer reactors are usually used and the silicon wafers are processed individually since this results in a good epitaxial layer thickness regularity. The uniformity of the layer thickness can be established by various measures, for example by altering the gas flows (H2, SiHCl3), by incorporating and adjusting gas inlet devices (injectors), by changing the deposition temperature, or by modifications to the susceptor.
In epitaxy it is furthermore customary, after one or more epitaxial depositions on silicon wafers, to carry out an etching treatment of the susceptor without a substrate, in the course of which the susceptor and also other parts of the process chamber are freed of silicon deposits. This etch, using hydrogen chloride (HCl), for example, is often carried out after the processing of only a small number of silicon wafers (after 1 to 5 silicon wafers) in the case of single wafer reactors, and is not carried out in part until after the processing of more silicon wafers (after 10 to 20 silicon wafers) in the case of depositing thin epitaxial layers. Usually, only an HCl etching treatment or else an HCl etching treatment followed by brief coating of the susceptor is performed.
The production of epitaxially coated silicon wafers with good global flatness proves to be extremely difficult since, as mentioned above, a concavely polished silicon wafer is usually present as the substrate. In the prior art, after the epitaxy, the global flatness and also the local flatness of the epitaxially coated silicon wafer have usually deteriorated compared with those of the concavely polished silicon wafer. This is associated, inter alia, with the fact that the deposited epitaxial layer itself also has a certain irregularity.
Although the deposition of a thicker epitaxial layer in the center of the concavely polished silicon wafer, where the thickness of said layer would have to decrease outward in the direction of the edge of the silicon wafer, could compensate for the originally concave form of the silicon wafer and thus also improve the global flatness of the silicon wafer, this is not considered in the epitaxy of silicon wafers since an important specification of an epitaxially coated silicon wafer, namely a limit for the regularity of the epitaxial layer, cannot be exceeded.
DE 102005045339 A1 discloses a method for producing epitaxially coated silicon wafers in which a multiplicity of silicon wafers which are polished at least on their front sides are successively coated individually in an epitaxy reactor by a procedure in which a silicon wafers is placed on a susceptor in the epitaxy reactor, and pretreated under a hydrogen atmosphere at a first hydrogen flow rate of 20-100 slm in a first step, and with addition of an etching medium to the hydrogen atmosphere at a second, reduced hydrogen flow rate of 0.5-10 slm in a second step, the wafer is subsequently coated epitaxially on its polished front side and removed from the epitaxy reactor, and an etching treatment of the susceptor is furthermore effected after a specific number of epitaxial coatings.
DE 102005045339 A1 also discloses a silicon wafer having a front side and a rear side, wherein at least its front side is polished and an epitaxial layer is applied at least on its front side, and which has a global flatness value GBIR of 0.07-0.3 μm, relative to an edge exclusion of 2 mm. The comparatively good geometry of this epitaxially coated silicon wafer results from the fact that the reduction of the hydrogen flow rate in the second step of the pretreatment with addition of an etching medium makes it possible to etch away material at the edge of the silicon wafer in a targeted manner and to globally level the silicon wafer before the epitaxial-coating step. Disadvantages of the method disclosed in DE 102005045339 are that although the reduced hydrogen flow rate intensifies the etching effect at the edge of the polished wafer, the gas flow over the semiconductor wafer is not laminar. It has been shown that precisely this flow impedes further optimization of the global flatness below the GBIR value of 0.07 μm disclosed in DE 102005045339 A1.
US 2008/0182397 A1 discloses an epitaxy reactor which provides different gas flows in a so-called “inner zone” and a so-called “outer zone”. For a wafer having a diameter of 300 mm, the “inner zone” is specified as a central region of the 300 mm wafer having a diameter of 75 mm. The setting of the different gas flows in the reactor is effected by setting the diameter of the gas pipes; thus, e.g. reducing the pipe diameter also reduces the gas flow in the direction of one of the two zones. Such gas distribution systems are commercially available from Applied Materials Inc. under the name Epi Centura Accusett™ (Epi Centura is the name of the epitaxy reactor from Applied Materials Inc.). As an alternative, for controlling the gas flows it is also possible to use so-called “Mass Flow Controllers” or similar devices for regulating the flow. The gas distribution in inner and outer zones is designated by I/O in US 2008/0182397 A1. This notation will also be used in the context of the present invention. US 2008/0182397 A1 specifies two ranges for gas distribution I/O: firstly a range of I/O=0.2-1.0 during the epitaxial coating and secondly an I/O of 1.0-6.0 during the etching step (substrate pretreatment).
US 2008/0245767 A1 discloses a method in which a contaminated or damaged layer of a substrate is removed by means of an etching gas in order to uncover a substrate surface. This cleaned substrate can subsequently be epitaxially coated. The flow rate of the etching gas is 0.01-15 slm. If an inert gas (inert with respect to the substrate material, e.g. silicon) such as hydrogen or else nitrogen, argon, helium or the like is supplied, the flow rate thereof is 1-100 slm. The temperature of the substrate is 600-850° C. values of 1.0-7.0 (5/5-35/5) is specified as I/O ratio of the hydrogen flow.
US 2007/0010033 A1 discloses influencing the thickness of an epitaxially deposited layer by regulating the gas distribution in an inner and an outer zone. As mentioned above, however, the deposition of a thicker epitaxial layer in the center of the concavely polished silicon wafer, in order to compensate for the initial geometry of the polished wafer, is unsuitable since the specification of the layer thickness uniformity of the epitaxial layer would thereby be exceeded.